1. Field of the Invention
The present invention relates to a lateral, bipolar transistor of the type formed in a semiconductor on an insulator. More particularly, this invention relates to a high speed, high gain bipolar transistor which may be manufactured without any additional masking or doping steps to those used in making standard CMOS devices, and is compatible with standard CMOS digital circuitry.
2. Description of the Related Art
Bipolar transistors and Metal-Oxide-Semiconductor (MOS) devices have historically been viewed as being separate and distinct types of devices, each having its own advantages and disadvantages.
A major advantage of bipolar devices is their ability to handle higher speeds at a higher power level than standard MOS devices. However, conventional bipolar devices typically have a fixed, low gain when compared to the idealized devices, which may be a disadvantage in many circuits since additional components may be needed to achieve a high gain. Also, many bipolars consume relatively large areas when compared to their MOS counterparts, making them unsuitable for certain applications. This tends to lower packing density and can also degrade the speed of the devices.
The slow speed of conventional bipolar transistors is in part caused by the existence of large parasitic capacitances between active regions in those bipolars that use a vertical geometry. The use of a Semiconductor-On-Insulator (SOI) structure tends to reduce these parasitic capacitances, and thereby increase the speed of such devices. Some of the advantages and characteristics of using an insulator, and particularly sapphire, are discussed in Vasudev (1986), "Silicon-OnSapphire Heteroepitaxy", Epitaxial Silicon Technology, Chapter 4, Academic Press, Inc.
A number of ways are known to reliably manufacture SOI Integrated Circuits (ICs), many of which are discussed in IEEE Circuits and Devices Magazine, July, 1987, Vol. 3, No. 4. Current techniques include Separation by Implanted Oxygen (SIMOX), scaled dielectric isolation, wafer bonding, Double Solid Phase Epitaxy (DSPE), Zone-Melting Recrystallization (ZMR), and the solid state epitaxy and regrowth (SPEAR) process discussed in U.S. Pat. No. 4,509,990 to Vasudev and assigned to Hughes Aircraft Company, the assignee of the present invention. For a general discussion of techniques for constructing MOS SOI circuits, see Scott et al., "CMOS Technology", VLSI Handbook, Chapter 10, Academic Press (1985).
Bipolars are typically of either vertical or lateral design. A typical lateral bipolar transistor using bulk silicon is disclosed in U.S. Pat. No. 4,435,225 issued Mar. 6, 1984 to Robert L. Berry et al. This device is slow, due to the large capacitances in the emitter-base and collector-base junctions. It also has a low gain as a result of losses arising from the high parasitics associated with the use of a silicon substrate is used without an insulation layer. FIGS. 1a and 1b depict cross-sections of typical prior art vertical and lateral bipolar devices, respectively.
As expected from their architecture, vertical bipolars such as the planar device shown in FIG. 1a typically have lower diffusion efficiencies, and require more isolation than lateral devices to prevent the formation of parasitic transistors or leakage currents flowing between adjacent, active devices. Of course, other types of devices need such isolation, including standard Complementary Metal Oxide Semiconductor (CMOS) components. Parasitic transistors are particularly a problem in Very Large Scale Integrated Chips (VLSICs) because the components are closely packed. The isolation of circuit components requires additional manufacturing steps, and increases the cost of the chip.
An increase in the size of the emitter-base and collector-base junctions in bipolar devices also has a tendency to decrease the cutoff bandwidth or maximum frequency of the device, due to an increase in parasitic capacitances with increased junction size. As shown by comparing FIGS. 1a and 1b, lateral bipolars typically have smaller junctions than vertical bipolars, and thus higher cutoff bandwidths.
Referring now to FIG. la, the emitter-base junction 10a of a vertical bipolar transistor is formed at the junction of emitter 11a and base 12a. Junction 10a is smaller than the corresponding emitter-base junction 10b of the lateral bipolar transistor shown in FIG. 1b. Junction 10b is formed between emitter 11b and base 12b.
Similarly, collector-base junction 13a in FIG. 1a forms the junction between collector 14a and base 12a. It is smaller in size than its counterpart, collector-base junction 13b in FIG. 1b. Junction 13b is formed at the interface of collector 14b and base 12b. The entire lateral device depicted in FIG. 1b is formed on a insulating substrate 15b. Regardless of whether a vertical or lateral bipolar device is considered, it is desirable to restrict the size of the junctions to make the device suitable for higher frequency applications. SPEAR, DSPE and standard SOS processes.
Lateral and vertical bipolars also differ in that lateral bipolars typically have higher base resistances than their vertical counterparts, resulting in lower common emitter gains. It is desirable to reduce the base resistance in a lateral bipolar by proper design and control of surface potential in order to increase its gain.
To make use of the advantages of bipolar and MOS devices, both types of devices have been manufactured on the same integrated circuit chip using vertical bipolars. Such so-called BIMOS circuits are difficult and expensive to reliably manufacture because one must generally use both bipolar and MOS masking and doping steps during the manufacturing process. Besides the increased expense involved with each additional manufacturing step, the probability of manufacturing defects in an IC increases with the number of steps.
BIMOS chips have also been made using lateral bipolars and CMOS devices on a bulk silicon substrate. However, these circuits are not satisfactory due to the poor frequency response of lateral bipolars when formed on a silicon substrate without an insulation layer.
A voltage controlled lateral bipolar-MOS transistor fabricated on an insulated substrate, and having a gate separated from the top surface of the base by a oxide layer, is disclosed in an article by the present inventor, "Recent Advances in Solid-Phase Epitaxial Recrystalization of SOS with Applications to CMOS and Bipolar Devices," IEEE Circuits and Devices Magazine, Vol. 3, No. 4, July, 1987, pages 17-19. Graphs of the common emitter current gain as a function of collector current for this device are presented in FIG. 1c for SOS npn lateral bipolar-MOS transistors fabricated by the SPEAR, DSPE and standard SOS processes.